In the prior art, there is the semiconductor device having such a structure that a semiconductor chip is sealed with a resin substrate and wiring layers are connected to connection electrodes of the semiconductor chip. In such semiconductor device, the wiring layers are connected directly to the connection electrodes of the semiconductor chip, therefore the solder bumps used to flip-chip mount the semiconductor chip can be omitted and thus a thickness reduction can be achieved. Accordingly, the wiring paths in the semiconductor device can be shortened, so that the structure that is effective in improving the power supply characteristics can be provided because an inductance of the wirings can be reduced.
The technology similar to such semiconductor device is disclosed in Patent Literature 1 (WO 02/15266 A2) and Patent Literature 2 (WO 02/33751 A2).
As explained in the column of the related art described later, in the semiconductor device in the related art, the semiconductor chip is temporarily fixed onto the supporting member via the pressure-sensitive adhesive sheet to direct the connection electrodes downward, and then the periphery and back surface sides of the semiconductor chip are sealed with a resin. Then, the supporting member and the pressure-sensitive adhesive sheet are removed, and then the build-up wiring connected to the connection electrodes of the semiconductor chip is formed.
In the related art, when the semiconductor chip is sealed with the resin, such a problem arises that the resin permeates the connection electrodes of the semiconductor chip through the boundary between the semiconductor chip and the pressure-sensitive adhesive sheet and the connection electrodes are contaminated. In the case that the resin permeates the connection electrodes of the semiconductor chip, in forming the build-up wirings, the permeating resin easily constitutes the residue in the via hole. Therefore, the connection failure between the semiconductor chip and the build-up wiring is easily caused.